Freescale’s Scalable Controller Area Network (S12MSCANV3)
In cases of more than one buffer having the same lowest priority, the message buffer with the lower index
number wins.
Module Base + 0x00XD
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
PRIO7
W
PRIO6
PRIO5
PRIO4
PRIO3
PRIO2
PRIO1
PRIO0
Reset:
0
0
0
0
0
0
0
0
Figure 8-36. Transmit Buffer Priority Register (TBPR)
1. Read: Anytime when TXEx flag is set (see Section 8.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the
corresponding transmit buffer is selected in CANTBSEL (see Section 8.3.2.11, “MSCAN Transmit Buffer Selection Register
(CANTBSEL)”)
Write: Anytime when TXEx flag is set (see Section 8.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the
corresponding transmit buffer is selected in CANTBSEL (see Section 8.3.2.11, “MSCAN Transmit Buffer Selection Register
(CANTBSEL)”)
8.3.3.5
Time Stamp Register (TSRH–TSRL)
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active
transmit or receive buffer right after the EOF of a valid message on the CAN bus (see Section 8.3.2.1,
“MSCAN Control Register 0 (CANCTL0)”). In case of a transmission, the CPU can only read the time
stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
Module Base + 0x00XE
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
W
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
Reset:
x
x
x
x
x
x
x
x
Figure 8-37. Time Stamp Register — High Byte (TSRH)
1. Read: Anytime when TXEx flag is set (see Section 8.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the
corresponding transmit buffer is selected in CANTBSEL (see Section 8.3.2.11, “MSCAN Transmit Buffer Selection Register
(CANTBSEL)”)
Write: Unimplemented
Module Base + 0x00XF
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
W
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
Reset:
x
x
x
x
x
x
x
x
Figure 8-38. Time Stamp Register — Low Byte (TSRL)
S12P-Family Reference Manual, Rev. 1.13
284
Freescale Semiconductor
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