S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.12 S12CPMU COP Timer Arm/Reset Register (CPMUARMCOP)
This register is used to restart the COP time-out period.
0x003F
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
0
0
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Reset
Figure 7-15. S12CPMU CPMUARMCOP Register
Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period
write $55 followed by a write of $AA. These writes do not need to occur back-to-back, but the
sequence ($55, $AA) must be completed prior to COP end of time-out period to avoid a COP reset.
Sequences of $55 writes are allowed. When the WCOP bit is set, $55 and $AA writes must be done
in the last 25% of the selected time-out period; writing any value in the first 75% of the selected
period will cause a COP reset.
7.3.2.13 High Temperature Control Register (CPMUHTCTL)
The CPMUHTCTL register configures the temperature sense features.
0x02F0
7
6
5
4
3
2
1
0
R
W
0
0
0
HTDS
VSEL
HTE
HTIE
HTIF
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Read: Anytime
Write: VSEL, HTE, HTIE and HTIF are write anytime, HTDS is read only
S12P-Family Reference Manual, Rev. 1.13
220
Freescale Semiconductor
FREESCALE [ Freescale ]
