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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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S12S Debug Module (S12SDBGV2)  
6.5.2  
Scenario 1  
A trigger is generated if a given sequence of 3 code events is executed.  
Figure 6-27. Scenario 1  
SCR2=0010  
SCR3=0111  
SCR1=0011  
M0  
M2  
M1  
Final State  
State3  
State2  
State1  
Scenario 1 is possible with S12SDBGV1 SCR encoding  
6.5.3  
Scenario 2  
A trigger is generated if a given sequence of 2 code events is executed.  
Figure 6-28. Scenario 2a  
SCR2=0101  
SCR1=0011  
M2  
M1  
Final State  
State2  
State1  
A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into  
a range (COMPA,COMPB configured for range mode). M1 is disabled in range modes.  
Figure 6-29. Scenario 2b  
SCR2=0101  
SCR1=0111  
M2  
M01  
Final State  
State2  
State1  
A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry  
into a range (COMPA,COMPB configured for range mode)  
Figure 6-30. Scenario 2c  
SCR2=0011  
SCR1=0010  
M0  
M2  
Final State  
State2  
State1  
All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding  
S12P-Family Reference Manual, Rev. 1.13  
190  
Freescale Semiconductor  
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