System Integration Module (SIM)
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO CGM, OSC)
SIM
COUNTER
COP CLOCK
ICLK (FROM OSC)
CGMOUT (FROM CGM)
÷ 2
V
CLOCK
CONTROL
DD
CLOCK GENERATORS
INTERNAL CLOCKS
INTERNAL
PULLUP
DEVICE
RESET
PIN LOGIC
LVI (FROM LVI MODULE)
POR CONTROL
MASTER
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
RESET
RESET PIN CONTROL
CONTROL
SIM RESET STATUS REGISTER
COP (FROM COP MODULE)
RESET
INTERRUPT SOURCES
CPU INTERFACE
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 7-1. SIM Block Diagram
Addr.
Register Name
Bit 7
R
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
Bit 0
R
Read:
Write:
Reset:
SBSW
NOTE
0
SIM Break Status Register
(SBSR)
$FE00
0
0
Note: Writing a logic 0 clears SBSW.
Read:
SIM Reset Status Register
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
$FE01
$FE03
Write:
(SRSR)
POR:
1
BCFE
0
0
0
0
0
0
0
0
Read:
SIM Break Flag Control
Write:
R
R
R
R
R
R
R
Register (SBFCR)
Reset:
Figure 7-2. SIM I/O Register Summary
MC68HC908AP Family Data Sheet, Rev. 4
98
Freescale Semiconductor
FREESCALE [ Freescale ]
