SIM Bus Clock Control and Generation
Read:
Write:
IF6
R
IF5
R
IF4
R
IF3
R
IF2
R
IF1
R
0
R
0
R
Interrupt Status Register 1
(INT1)
$FE04
$FE05
$FE06
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
IF14
R
IF13
R
IF12
R
IF11
R
IF10
R
IF9
R
IF8
R
IF7
R
Interrupt Status Register 2
(INT2)
0
0
0
0
0
0
0
0
0
IF21
R
IF20
R
IF19
R
IF18
R
IF17
R
IF16
R
IF15
R
Interrupt Status Register 3
(INT3)
R
0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-2. SIM I/O Register Summary
7.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 7-3. This clock can
come from either an external oscillator or from the on-chip PLL. (See Chapter 6 Clock Generator Module
(CGM).)
OSC2
OSCCLK
TO TBM
OSCILLATOR (OSC) MODULE
CGMXCLK
TO TIM, ADC
OSC1
ICLK
CGMOUT
SIMDIV2
SIM COUNTER
SIMOSCEN
STOP MODE CLOCK
ENABLE SIGNALS
FROM CONFIG2
SYSTEM INTEGRATION MODULE
IT12
TO REST
OF MCU
CGMRCLK
BUS CLOCK
÷ 2
IT23
TO REST
OF MCU
GENERATORS
PHASE-LOCKED LOOP (PLL)
PTB0
MONITOR MODE
USER MODE
CGMVCLK
TO PWM
Figure 7-3. CGM Clock Signals
7.2.1 Bus Timing
In user mode, the internal bus frequency is either the oscillator output (CGMXCLK) divided by four or the
divided PLL output (CGMPCLK) divided by four.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
99
FREESCALE [ Freescale ]
