Central Processor Unit (CPU)
4.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by:
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU
to normal operation if the break interrupt has been deasserted.
4.7 Instruction Set Summary
Table 4-1 provides a summary of the M68HC08 instruction set.
4.8 Opcode Map
The opcode map is provided in Table 4-2.
Table 4-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Add with Carry
A ← (A) + (M) + (C)
o o – o o o
SP1
SP2
9EE9 ff
9ED9 ee ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Add without Carry
A ← (A) + (M)
o o – o o o
SP1
SP2
9EEB ff
9EDB ee ff
AIS #opr
AIX #opr
Add Immediate Value (Signed) to SP
Add Immediate Value (Signed) to H:X
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
–
–
–
–
–
–
–
–
–
–
– IMM
– IMM
A7
AF
ii
ii
2
2
MC68HC908AP Family Data Sheet, Rev. 4
60
Freescale Semiconductor
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