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MC908AP32CFAE 参数 Datasheet PDF下载

MC908AP32CFAE图片预览
型号: MC908AP32CFAE
PDF下载: 下载PDF文件 查看货源
内容描述: [MC908AP32CFAE]
分类和应用:
文件页数/大小: 325 页 / 4102 K
品牌: FREESCALE [ Freescale ]
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Arithmetic/Logic Unit (ALU)  
After the I bit is cleared, the highest-priority interrupt request is serviced first.  
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the  
interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the  
clear interrupt mask software instruction (CLI).  
N — Negative flag  
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation  
produces a negative result, setting bit 7 of the result.  
1 = Negative result  
0 = Non-negative result  
Z — Zero flag  
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation  
produces a result of $00.  
1 = Zero result  
0 = Non-zero result  
C — Carry/Borrow Flag  
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the  
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test  
and branch, shift, and rotate — also clear or set the carry/borrow flag.  
1 = Carry out of bit 7  
0 = No carry out of bit 7  
4.4 Arithmetic/Logic Unit (ALU)  
The ALU performs the arithmetic and logic operations defined by the instruction set.  
Refer to the CPU08 Reference Manual (Freescale document order number CPU08RM/AD) for a  
description of the instructions and addressing modes and more detail about the architecture of the CPU.  
4.5 Low-Power Modes  
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.  
4.5.1 Wait Mode  
The WAIT instruction:  
Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from  
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.  
Disables the CPU clock  
4.5.2 Stop Mode  
The STOP instruction:  
Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After  
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.  
Disables the CPU clock  
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.  
MC68HC908AP Family Data Sheet, Rev. 4  
Freescale Semiconductor  
59  
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