Electrical Specifications
Table 22-8. DC Electrical Characteristics (3V)
Characteristic(1)
Typ(2)
Symbol
Min
Max
Unit
Pullup resistors(10)
PTD[0:7]
RST, IRQ1, IRQ2
RPU1
RPU2
21
21
27
27
39
39
kΩ
kΩ
Low-voltage inhibit, trip falling voltage1(11)
Low-voltage inhibit, trip rising voltage1(10)
Low-voltage inhibit, trip voltage2(10)
VTRIPF1
VTRIPR1
VTRIPF2
VREG
2.25
2.35
2.25
2.25
2.45
2.55
2.45
2.50
2.65
2.75
2.65
2.75
V
V
V
V
(10), (12)
VREG
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. At VDD = 3V, an on-chip charge pump is activated for the VREG regulator, therefore some IDD values will appear higher
than the IDD values at VDD = 5V.
4. Run (operating) IDD measured using external 16MHz/32MHz clock to OSC1; all inputs 0.2 V from rail; no dc loads; less
than 100 pF on all outputs; CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects run IDD
measured with all modules enabled.
;
5. Wait IDD measured using external 16MHz/32MHz clock to OSC1; all inputs 0.2 V from rail; no dc loads; less than 100 pF
on all outputs. CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait IDD
6. STOP IDD measured with external 32.768kHz clock to OSC1; no port pins sourcing current.
7. STOP IDD measured with OSC1 grounded; no port pins sourcing current.
.
8. Maximum is highest voltage that POR is guaranteed. The rearm voltage is triggered by VREG
.
9. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
10. RPU1 and RPU2 are measured at VDD = 5.0V
11. Values are not affected by operating VDD; they are the same for 3V and 5V.
12. Measured from VDD = VTRIPF1 (Min) to 5.5 V.
22.10 3V Control Timing
Table 22-9. Control Timing (3V)
Characteristic(1)
Symbol
Min
—
Max
8
Unit
MHz
ns
Internal operating frequency(2)
fOP
RST input pulse width low(3)
tIRL
750
—
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this in-
formation.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
MC68HC908AP Family Data Sheet, Rev. 4
304
Freescale Semiconductor
FREESCALE [ Freescale ]
