Table 8-1. Monitor Mode Signal Requirements and Options
Address
$FFFE/
$FFFF
External
Clock(2)
PTA0
(1)
Bus
Frequency
Baud
Rate
IRQ1
RST
PTA2 PTA1
PTB0
PLL
COP
Comment
No operation until
reset goes high
X
GND
X
X
0
X
1
X
1
X
X
0
X
Disabled
0
PTA1 and PTA2
voltages only
required if
VDD
or
VTST
4.9152
MHz
2.4576
MHz
(3)
X
0
1
OFF Disabled
9600
VTST
IRQ1 = VTST
;
PTB0 determines
frequency divider
PTA1 and PTA2
voltages only
required if
VDD
or
VTST
9.8304
MHz
2.4576
MHz
(3)
X
0
1
1
OFF Disabled
OFF Disabled
9600
VTST
IRQ1 = VTST
;
PTB0 determines
frequency divider
Blank
"$FFFF"
9.8304
MHz
2.4576
MHz
External frequency
always divided by 4
VDD
VDD
X
X
X
X
1
1
X
X
9600
9600
PLL enabled
(BCS set)
in monitor mode
Blank
"$FFFF"
32.768
kHz
2.4576
MHz
VDD
GND
ON
Disabled
Enabled
Enters user
mode — will
encounter an illegal
address reset
VDD
or
GND
Blank
"$FFFF"
VTST
X
X
X
X
X
X
X
X
X
X
—
—
OFF
—
—
VDD
or
VDD
or
Not Blank
OFF
Enabled
Enters user mode
VTST
GND
1. PTA0 = 1 if serial communication; PTA0 = 0 if parallel communication
2. External clock is derived by a 32.768kHz crystal or a 4.9152/9.8304MHz off-chip oscillator.
3. Monitor mode entry by IRQ1= VTST, a 4.9152/9.8304 MHz off-chip oscillator must be used. The MCU internal crystal oscillator circuit is by-
passed.
FREESCALE [ Freescale ]
