Monitor ROM (MON)
RST
0.1 µF
HC908AP
V
DD
V
DD
V
DDA
0.1 µF
V
REFH
V
REG
V
REFL
V
V
SS
REG
4.9152MHz/9.8304MHz
(50% DUTY)
V
SSA
OSC1
CGMXFC
0.01 µF
10k
MUST BE USED IF SW2 IS AT POSITION C.
CONNECT TO OSC1, WITH OSC2 UNCONNECTED.
0.033 µF
EXT OSC
4.9152MHz
OSC1
OSC2
6–30 pF
1M
MAX232
V
DD
1
16
15
V
C1+
6–30 pF
CC
+
+
+
1 µF
1 µF
1 µF
3
4
1 µF
C1–
C2+
GND
+
XTAL CIRCUIT
V
V
C
2
6
TST
SW2
V+
V–
(SEE NOTE 1)
1 k
DD
IRQ1
PTA0
8.5 V
D
5
V
DD
C2–
1 µF
10 k
+
10k
74HC125
6
DB9
5
10
9
2
3
7
8
74HC125
3
4
V
V
DD
2
DD
1
5
10k
10k
PTA1
PTB0
PTA2
SW1
A
B
(SEE NOTE 2)
NOTES:
1. Monitor mode entry method:
SW2: Position C — High voltage entry (V
10 k
); must use external OSC
10 k
TST
Bus clock depends on SW1 (note 2).
SW2: Position D — Reset vector must be blank ($FFFE:$FFFF = $FF)
Bus clock = 1.2288MHz.
2. Affects high voltage entry to monitor mode only (SW2 at position C):
SW1: Position A — Bus clock = OSC1
SW1: Position B — Bus clock = OSC1
4
2
5. See Table 22-4 for V
voltage level requirements.
TST
Figure 8-1. Monitor Mode Circuit
MC68HC908AP Family Data Sheet, Rev. 4
116
Freescale Semiconductor
FREESCALE [ Freescale ]
