Freescale Semiconductor, Inc.
Capture/Compare Timer
Timer Operation
Addr.
Register Name
Bit 7
ICIE
0
6
5
4
3
2
1
Bit 0
Read:
Timer Control Register
OCIE
TOIE
0
0
0
IEDG
OLVL
$0012
(TCR) Write:
See page 94.
Reset:
0
0
0
0
0
0
0
0
U
0
0
0
Read: ICF
OCF
TOF
Timer Status Register
(TSR) Write:
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
See page 96.
Reset:
U
U
U
0
0
0
0
0
Read: Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Input Capture Register
High (ICRH) Write:
See page 100.
Reset:
Unaffected by reset
Bit 4 Bit 3
Read: Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
Input Capture Register
Low (ICRL) Write:
See page 100.
Reset:
Unaffected by reset
Bit 12 Bit 11
Unaffected by reset
Bit 4 Bit 3
Output Compare Register Read:
Bit 15
Bit 7
Bit 14
Bit 13
Bit 10
High (OCRH)
See page 101.
Write:
Reset:
Read:
Output Compare Register
Bit 6
Bit 5
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
Low (OCRL) Write:
See page 101.
Reset:
Unaffected by reset
Bit 12 Bit 11
Read: Bit 15
Bit 14
Bit 13
Bit 10
Timer Register High
(TRH) Write:
See page 97.
Reset:
Reset initializes TRH to $FF
Bit 4 Bit 3
Read: Bit 7
Bit 6
Bit 14
Bit 6
Bit 5
Bit 13
Bit 5
Bit 2
Bit 10
Bit 2
Bit 1
Bit 9
Bit 1
Bit 0
Bit 8
Bit 0
Timer Register Low
(TRL) Write:
See page 97.
Reset:
Reset initializes TRL to $FC
Bit 12 Bit 11
Read: Bit 15
Alternate Timer Register
High (ATRH) Write:
See page 99.
Reset:
Reset initializes ATRH to $FF
Bit 4 Bit 3
Read: Bit 7
Alternate Timer Register
Low (ATRL) Write:
See page 99.
Reset:
Reset initializes ATRL to $FC
U = Unaffected
= Unimplemented
Figure 8-2. Timer I/O Register Summary
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Capture/Compare Timer
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