Freescale Semiconductor, Inc.
FLASH-2 Memory
FLASH Control Register
Programming tools are available from Motorola. Contact a local Motorola
representative for more information.
NOTE: A security feature prevents viewing of the FLASH contents.(1)
5.4 FLASH Control Register
The FLASH-2 control register (FLCR2) controls FLASH-2 program,
erase, and margin read operations.
Address: $FE11
Bit 7
FDIV1
0
6
FDIV0
0
5
BLK1
0
4
BLK0
0
3
2
1
Bit 0
PGM
0
Read:
Write:
Reset:
HVEN MARGIN ERASE
0
0
0
Figure 5-1. FLASH-2 Control Register (FLCR2)
FDIV1 — Frequency Divide Control Bit
This read/write bit together with FDIV0 selects the factor by which the
charge pump clock is divided from the system clock. See 5.5 FLASH
Charge Pump Frequency Control.
FDIV0 — Frequency Divide Control Bit
This read/write bit together with FDIV1 selects the factor by which the
charge pump clock is divided from the system clock. See 5.5 FLASH
Charge Pump Frequency Control.
BLK1 — Block Erase Control Bit
This read/write bit together with BLK0 allows erasing of blocks of
varying size. See 5.6 FLASH Erase Operation for a description of
available block sizes.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
MC68HC908AS60 — Rev. 1.0
Technical Data
FLASH-2 Memory
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