Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
I/O Registers
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the
stop bit. FE generates an SCI error CPU interrupt request if the FEIE
bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
17.9.5 SCI Status Register 2
SCI status register 2 contains flags to signal these conditions:
• Break character detected
• Incoming data
Address: $0017
Bit 7
6
5
4
0
3
0
2
0
1
Bit 0
RPF
Read:
Write:
Reset:
BKF
0
0
0
0
0
= Unimplemented
Figure 17-14. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break
character on the RxD pin. In SCS1, the FE and SCRF bits are also
set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared.
BKF does not generate a CPU interrupt request. Clear BKF by
MC68HC908AS60 — Rev. 1.0
Technical Data
Serial Communications Interface (SCI)
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