Clock Generator Module (CGM)
6.4.3 PLL Analog Ground Pin (V
)
SSA
V
is a ground pin used by the analog portions of the PLL. Connect the V
pin to the same voltage
SSA
SSA
potential as the V pin.
SS
NOTE
carefully for maximum noise immunity and place bypass
Route V
SSA
capacitors as close as possible to the package.
6.4.4 Oscillator Output Frequency Signal (CGMXCLK)
CGMXCLK is the oscillator output signal. It runs at the full speed of the oscillator, and is generated directly
from the crystal oscillator circuit, the RC oscillator circuit, or the internal oscillator circuit.
6.4.5 CGM Reference Clock (CGMRCLK)
CGMRCLK is a buffered version of CGMXCLK, this clock is the reference clock for the phase-locked-loop
circuit.
6.4.6 CGM VCO Clock Output (CGMVCLK)
CGMVCLK is the clock output from the VCO.
6.4.7 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks.
CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by two or the divided VCO clock,
CGMPCLK, divided by two.
6.4.8 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
6.5 CGM Registers
The following registers control and monitor operation of the CGM:
•
•
•
•
•
PLL control register (PCTL)
(See 6.5.1 PLL Control Register.)
PLL bandwidth control register (PBWC)
(See 6.5.2 PLL Bandwidth Control Register.)
PLL multiplier select registers (PMSH and PMSL)
(See 6.5.3 PLL Multiplier Select Registers.)
PLL VCO range select register (PMRS)
(See 6.5.4 PLL VCO Range Select Register.)
PLL reference divider select register (PMDS)
(See 6.5.5 PLL Reference Divider Select Register.)
MC68HC908AP Family Data Sheet, Rev. 4
88
Freescale Semiconductor
FREESCALE [ Freescale ]
