I/O Signals
6.3.9 CGM External Connections
In its typical configuration, the CGM requires up to four external components.
Figure 6-3 shows the external components for the PLL:
•
•
Bypass capacitor, C
Filter network
BYP
Care should be taken with PCB routing in order to minimize signal cross talk and noise. (See 6.8
Acquisition/Lock Time Specifications for routing information, filter network and its effects on PLL
performance.)
MCU
CGMXFC
V
V
DDA
SSA
V
DD
1 kΩ
C
0.1 µF
BYP
10 nF
0.22 µF
Note: Filter network in box can be replaced with a 0.47µF capacitor, but will degrade stability.
Figure 6-3. CGM External Connections
6.4 I/O Signals
The following paragraphs describe the CGM I/O signals.
6.4.1 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is
connected to this pin. (See Figure 6-3.)
NOTE
To prevent noise problems, the filter network should be placed as close to
the CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the network.
6.4.2 PLL Analog Power Pin (V
)
DDA
V
is a power pin used by the analog portions of the PLL. Connect the V
pin to the same voltage
DDA
DDA
potential as the V pin.
DD
NOTE
carefully for maximum noise immunity and place bypass
Route V
DDA
capacitors as close as possible to the package.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
87
FREESCALE [ Freescale ]
