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MC68HC908AP64CFB 参数 Datasheet PDF下载

MC68HC908AP64CFB图片预览
型号: MC68HC908AP64CFB
PDF下载: 下载PDF文件 查看货源
内容描述: [MC68HC908AP64CFB]
分类和应用: 外围集成电路时钟
文件页数/大小: 325 页 / 1651 K
品牌: FREESCALE [ Freescale ]
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Functional Description  
Addr.  
Register Name  
Bit 7  
PLLIE  
0
6
5
PLLON  
1
4
3
2
1
Bit 0  
VPR0  
0
Read:  
Write:  
Reset:  
Read:  
PLLF  
BCS  
PRE1  
PRE0  
VPR1  
PLL Control Register  
(PTCL)  
$0036  
0
0
0
0
0
0
0
0
0
LOCK  
PLL Bandwidth Control  
AUTO  
ACQ  
R
$0037  
Register Write:  
(PBWC)  
Reset:  
Read:  
0
0
0
0
0
0
0
0
0
MUL11  
0
0
MUL10  
0
0
MUL9  
0
PLL Multiplier Select  
MUL8  
$0038  
Register High Write:  
(PMSH)  
Reset:  
Read:  
0
0
0
0
0
MUL0  
0
PLL Multiplier Select  
MUL7  
0
MUL6  
1
MUL5  
0
MUL4  
0
MUL3  
0
MUL2  
0
MUL1  
0
$0039  
Register Low Write:  
(PMSL)  
Reset:  
Read:  
PLL VCO Range Select  
VRS7  
VRS6  
VRS5  
VRS4  
VRS3  
0
VRS2  
0
VRS1  
0
VRS0  
0
$003A  
$003B  
NOTES:  
Register Write:  
(PMRS)  
Reset:  
Read:  
0
0
1
0
0
0
0
0
PLL Reference Divider  
RDS3  
RDS2  
RDS1  
0
RDS0  
1
Select Register Write:  
(PMDS)  
Reset:  
0
0
0
0
0
0
= Reserved  
= Unimplemented  
R
1. When AUTO = 0, PLLIE is forced clear and is read-only.  
2. When AUTO = 0, PLLF and LOCK read as clear.  
3. When AUTO = 1, ACQ is read-only.  
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.  
5. When PLLON = 1, the PLL programming register is read-only.  
6. When BCS = 1, PLLON is forced set and is read-only.  
Figure 6-2. CGM I/O Register Summary  
6.3.1 Oscillator Module  
The oscillator module provides two clock outputs CGMXCLK and CGMRCLK to the CGM module.  
CGMXCLK when selected, is driven to SIM module to generate the system bus clock. CGMRCLK is used  
by the phase-lock-loop to provide a higher frequency system bus clock. The oscillator module also  
provides the reference clock for the timebase module (TBM). See Chapter 5 Oscillator (OSC) for detailed  
oscillator circuit description. See Chapter 10 Timebase Module (TBM) for detailed description on TBM.  
6.3.2 Phase-Locked Loop Circuit (PLL)  
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending  
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes  
either automatically or manually.  
6.3.3 PLL Circuits  
The PLL consists of these circuits:  
Voltage-controlled oscillator (VCO)  
Reference divider  
Frequency pre-scaler  
Modulo VCO frequency divider  
MC68HC908AP Family Data Sheet, Rev. 4  
Freescale Semiconductor  
81  
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