Clock Generator Module (CGM)
OSCILLATOR (OSC) MODULE
See Chapter 5 Oscillator (OSC).
OSC2
OSC1
ICLK
To SIM (and COP)
To Timebase Module (TBM)
To ADC
OSCCLK
CGMXCLK
CGMRCLK
INTERNAL OSCILLATOR
RC OSCILLATOR
MUX
OSCSEL[1:0]
OSCCLK[1:0]
CRYSTAL OSCILLATOR
SIMOSCEN
From SIM
PHASE-LOCKED LOOP (PLL)
CGMRDV
CGMRCLK
CGMXFC
REFERENCE
DIVIDER
CGMOUT
To SIM
A
B
CLOCK
SELECT
CIRCUIT
1
÷ 2
BCS
S*
R
SIMDIV2
From SIM
*WHEN S = 1,
CGMOUT = B
RDS[3:0]
V
V
SSA
DDA
VPR[1:0]
VRS[7:0]
L
E
2
CGMPCLK
VOLTAGE
CONTROLLED
OSCILLATOR
PHASE
DETECTOR
LOOP
FILTER
PLL ANALOG
AUTOMATIC
MODE
CONTROL
CGMINT
To SIM
LOCK
DETECTOR
INTERRUPT
CONTROL
LOCK
AUTO
ACQ
PLLIE
PLLF
MUL[11:0]
PRE[1:0]
P
N
2
CGMVCLK
CGMVDV
FREQUENCY
DIVIDER
FREQUENCY
DIVIDER
Figure 6-1. CGM Block Diagram
MC68HC908AP Family Data Sheet, Rev. 4
80
Freescale Semiconductor
FREESCALE [ Freescale ]
