SCI Functional Description
CKS
SL
INTERNAL BUS
PRE- BAUD
SCALER DIVIDER
CGMXCLK
BUS CLOCK
A
÷ 16
SCI DATA REGISTER
X
B
SL = 0 => X = A
SL = 1 => X = B
SCP1
SCP0
SCR1
SCR2
SCR0
11-BIT
TRANSMIT
SHIFT REGISTER
H
8
7
6
5
4
3
2
1
0
L
SCI_TxD
M
PEN
PTY
PARITY
GENERATION
T8
DMATE
TRANSMITTER
CONTROL LOGIC
DMATE
SCTIE
SCTE
SCTE
SBK
DMATE
SCTE
LOOPS
ENSCI
TE
SCTIE
SCTIE
TC
TC
TCIE
TCIE
Figure 12-7. SCI Transmitter
12.5.2.2 Character Transmission
During an SCI transmission, the transmit shift register shifts a character out to the TxD pin. The IRSCI
data register (IRSCDR) is the write-only buffer between the internal data bus and the transmit shift
register. To initiate an SCI transmission:
1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in IRSCI control register 1
(IRSCC1).
2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in IRSCI control register
2 (IRSCC2).
3. Clear the SCI transmitter empty bit by first reading IRSCI status register 1 (IRSCS1) and then
writing to the IRSCDR.
4. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically loads the transmit shift register with
a preamble of logic 1s. After the preamble shifts out, control logic transfers the IRSCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the
transmit shift register. A logic 1 stop bit goes into the most significant bit position.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
187
FREESCALE [ Freescale ]
