Reset and System Initialization
ICLK
RST
IAB
VECT H VECT L
PC
Figure 7-4. External Reset Timing
7.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 ICLK cycles to allow resetting of external
peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see
Figure 7-5). An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or
POR (see Figure 7-6).
NOTE
For LVI or POR resets, the SIM cycles through 4096 + 32 ICLK cycles
during which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in
Figure 7-5.
IRST
RST PULLED LOW BY MCU
32 CYCLES
RST
32 CYCLES
ICLK
IAB
VECTOR HIGH
Figure 7-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
INTERNAL RESET
POR
Figure 7-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
7.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 + 32 ICLK cycles. Thirty-two ICLK cycles later, the CPU and memories are released from reset to
allow the reset vector sequence to occur.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
101
FREESCALE [ Freescale ]
