Freescale Semiconductor, Inc.
Resets and Interrupts
Highest
Power-on reset
(POR)
Priority
External
reset
Clock monitor fail
(CME = 1)
Lowest
Delay
(4064 cycles)
COP watchdog
timeout
(NOCOP = 0)
Load program counter
with contents of
$FFFE, $FFFF
Load program counter
with contents of
$FFFC, $FFFD
(vector fetch)
Load program counter
with contents of
$FFFA, $FFFB
(vector fetch)
(vector fetch)
Set S, X, and I bits
in CCR.
Reset MCU hardware
1A
Begin an instruction
sequence
X-bit in
CCR set?
Yes
No
Stack CPU registers.
XIRQ pin
low?
Set X and I bits.
Fetch vector at
$FFF4, $FFF5
Yes
No
1B
Technical Data
MC68HC11P2 — Rev 1.0
Resets and Interrupts
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