March 20, 1997 5:12 pm
Table 1:
#
1
1
2,3
5A
6
7
8
9
11
12
13
14
14A
15
16
17
18
Clock high to AS, DS asserted
Address, FC Valid to AS, DS Assert (read)
AS assert (Write)
Clock low to AS, DS negate
AS, DS Negated to Address FC Invalid
AS (and DS read) width asserted
DS width asserted, write
AS, DS width negate
Clock high to Control Bus Hi-z
AS, DS Negated to R/W Invalid
Clock high to R/W hi
Clock high to Address, Data Hi-z
Clock high to Address, FC invalid (Minimum)
Clock high to FC, address valid
EXTAL to Clock delay
Clock pulse width
Cycle period
tcyc
tcl,tch
tcd
tchfcadv
tchadz
tchafi
tchsl
tafcvsl
tclsn
tshafi
tsl
tdsl
tsh
tchca
tshrh
tchrh
Spec
No.
Description
Spec Name
UM
33MHz
Min
30
15
2
0
-
0
3
8
-
8
60
30
30
-
8
-
33MHz
Max
Freescale Semiconductor, Inc.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
11
27
25
-
15
-
15
-
-
-
-
25
-
15
Page 1 of 13
MC68302 Document
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