March 20, 1997 5:12 pm
Table 1:
#
83
84
109A
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
RW valid to clock high
Clock high to RW high
AS low to IAC high
AS high to IAC low
AS low to DTACK low (0 wait states)
Clock low to DTACK low (1 wait state)
AS high to DTACK high
DTACK high to DTACK hi-z
Clock low to UDS/LDS high
UDS/LDS low to clock high
AS inactive time
AS high to address hold time on write
Clock low to AS high
AS low to clock high
Address valid to AS low
Data out valid to DTACK low
108A
DS high to data out hold time
tdshdh
tdovdkl
tavasl
taslch
tclash
tashah
tash
tslch
tclsh
trwvch
tchrwh
tasliah
tashial
tasldtl
tcldtl
tashdth
tdthdtz
Spec
No.
Description
Spec Name
UM
33MHz
Min
0
10
8
15
-
0
1 clk
21
-
15
-
-
-
-
-
-
-
33MHz
Max
-
-
Freescale Semiconductor, Inc.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
-
-
25
-
-
-
20
-
20
21
21
25
15
20
10
Page 6 of 13
MC68302 Document
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