Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . .5
Part 8: General Purpose Input/Output
1.1. 56F8366/56F8166 Features . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment . 9
1.4. Architecture Block Diagram . . . . . . . . . . . . 10
1.5. Product Documentation . . . . . . . . . . . . . . . 14
1.6. Data Sheet Conventions . . . . . . . . . . . . . . 14
(GPIO) . . . . . . . . . . . . . . . . . . . . . . 137
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . .137
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . .138
8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . .138
Part 9: Joint Test Action Group (JTAG) . 143
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . .143
Part 2: Signal/Connection Descriptions . . .15
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18
Part 10: Specifications . . . . . . . . . . . . . . . 144
10.1. General Characteristics . . . . . . . . . . . . . .144
10.2. DC Electrical Characteristics . . . . . . . . . .148
10.3. AC Electrical Characteristics . . . . . . . . . .152
10.4. Flash Memory Characteristics . . . . . . . . .152
10.5. External Clock Operation Timing . . . . . . .153
10.6. Phase Locked Loop Timing . . . . . . . . . . .153
10.7. Crystal Oscillator Timing . . . . . . . . . . . . .154
10.8. External Memory Interface Timing . . . . . .154
10.9. Reset, Stop, Wait, Mode Select, and
Part 3: On-Chip Clock Synthesis (OCCS) . .38
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2. External Clock Operation . . . . . . . . . . . . . . 38
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Part 4: Memory Map . . . . . . . . . . . . . . . . . . .40
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . 41
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 44
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 48
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 49
4.7. Peripheral Memory Mapped Registers . . . . 50
4.8. Factory Programmed Memory . . . . . . . . . . 83
Interrupt Timing . . . . . . . . . . . . . .157
10.10. Serial Peripheral Interface (SPI) Timing .159
10.11. Quad Timer Timing . . . . . . . . . . . . . . . .162
10.12. Quadrature Decoder Timing . . . . . . . . . .163
10.13. Serial Communication Interface (SCI)
Timing . . . . . . . . . . . . . . . . . . . . .164
10.14. Controller Area Network (CAN) Timing .164
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . .165
10.16. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . .166
10.17. Equivalent Circuit for ADC Inputs . . . . . .169
10.18. Power Consumption . . . . . . . . . . . . . . . .169
Part 5: Interrupt Controller (ITCN) . . . . . . . .83
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3. Functional Description . . . . . . . . . . . . . . . . 83
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . 85
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . 85
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 86
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Part 11: Packaging . . . . . . . . . . . . . . . . . . 171
11.1. 56F8366 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . .171
11.2. 56F8166 Package and Pin-Out
Part 6: System Integration Module (SIM) .114
6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . 115
6.4. Operating Mode Register . . . . . . . . . . . . . 116
6.5. Register Descriptions . . . . . . . . . . . . . . . . 117
6.6. Clock Generation Overview . . . . . . . . . . . 132
6.7. Power-Down Modes Overview . . . . . . . . . 132
6.8. Stop and Wait Mode Disable Function . . . 133
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Information . . . . . . . . . . . . . . . . . .174
Part 12: Design Considerations . . . . . . . . 178
12.1. Thermal Design Considerations . . . . . . . .178
12.2. Electrical Design Considerations . . . . . . .179
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . .180
Part 13: Ordering Information . . . . . . . . . 181
Part 7: Security Features . . . . . . . . . . . . . .134
7.1. Operation with Security Enabled . . . . . . . 134
7.2. Flash Access Blocking Mechanisms . . . . 135
56F8366 Technical Data, Rev. 2.0
4
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
