Freescale Semiconductor, Inc.
FST (FSR)
BCLKT (BCLKR)
DT
1
2
3
4
5
6
7
8
DR
DON'T CARE
1
2
3
4
5
6
7
8
DON'T CARE
Figure 2a. Long Frame Sync (Transmit and Receive Have Individual Clocking)
FST (FSR)
BCLKT (BCLKR)
Freescale Semiconductor, Inc...
DT
1
2
3
4
5
6
7
8
DR
DON'T CARE
1
2
3
4
5
6
7
8
DON'T CARE
Figure 2b. Short Frame Sync (Transmit and Receive Have Individual Clocking)
IDL SYNC
(FST)
IDL CLOCK (BCLKT)
IDL TX (DT)
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
DON'T
IDL RX (DR)
DON'T CARE
1
2
3
4
5
6
7
8
CARE
1
2
3
4
5
6
7
8
DON'T
CARE
B1-CHANNEL (FSR = 0)
B2-CHANNEL (FSR = 1)
Figure 2c. IDL Interface — BCLKR = 1 (Transmit and Receive Have Common Clocking)
FSC (FST)
DCL (BCLKT)
D
(DT)
out
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
DON'T
D
(DR)
in
CARE
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
DON'T CARE
B1-CHANNEL (FSR = 0)
B2-CHANNEL (FSR = 1)
Figure 2d. GCI Interface — BCLKR = 0 (Transmit and Receive Have Common Clocking)
Figure 2. Digital Timing Modes for the PCM Data Interface
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