Freescale Semiconductor, Inc.
version algorithm. All of the analog circuitry involved in the
data conversion (the voltage reference, RDAC, CDAC, and
comparator) are implemented with a differential architecture.
The receive section includes the DAC described above, a
sample and hold amplifier, a 5–pole, 3400 Hz switched ca-
pacitor low–pass filter with sinX/X correction, and a 2–pole
active smoothing filter to reduce the spectral components of
the switched capacitor filter. The output of the smoothing fil-
ter is buffered by an amplifier, which is output at the RO+ and
RO– pins. These outputs are capable of driving a 4 kΩ load
differentially or a 2 kΩ load to the VAG pin. The MC14LC5480
also has a pair of power amplifiers that are connected in a
push–pull configuration. The PI pin is the inverting input to
the PO– power amplifier. The non–inverting input is internally
tied to the VAG pin. This allows this amplifier to be used in an
inverting gain circuit with two external resistors. The PO+
amplifier has a gain of minus one, and is internally con-
nected to the PO– output. This complete power amplifier cir-
cuit is a differential (push–pull) amplifier with adjustable gain
that is capable of driving a 300
Ω
load to +12 dBm. The
power amplifier may be powered down independently of the
rest of the chip by connecting the PI pin to VDD.
The DT output will remain in a high–impedance state for at
least two FST pulses after power–up.
MASTER CLOCK
Since this codec–filter design has a single DAC architec-
ture, the MCLK pin is used as the master clock for all analog
signal processing including analog–to–digital conversion,
digital–to–analog conversion, and for transmit and receive fil-
tering functions of this device. The clock frequency applied to
the MCLK pin may be 256 kHz, 512 kHz, 1.536 MHz,
1.544 MHz, 2.048 MHz, 2.56 MHz, or 4.096 MHz. This de-
vice has a prescaler that automatically determines the proper
divide ratio to use for the MCLK input, which achieves the re-
quired 256 kHz internal sequencing clock. The clocking re-
quirements of the MCLK input are independent of the PCM
data transfer mode (i.e., Long Frame Sync, Short Frame
Sync, IDL mode, or GCI mode).
DIGITAL I/O
The MC14LC5480 is pin selectable for Mu–Law or A–Law.
Table 1 shows the 8–bit data word format for positive and
negative zero and full scale for both companding schemes
(see Tables 3 and 4 at the end of this document for a com-
plete PCM word conversion table). Table 2 shows the series
of eight PCM words for both Mu–Law and A–Law that corre-
spond to a digital milliwatt. The digital mW is the 1 kHz cal-
ibration signal reconstructed by the DAC that defines the
absolute gain or 0 dBm0 Transmission Level Point (TLP) of
the DAC. The 0 dBm0 level for Mu–Law is 3.17 dB below the
maximum level for an unclipped tone signal. The 0 dBm0
level for A–Law is 3.14 dB below the maximum level for an
unclipped tone signal. The timing for the PCM data transfer is
independent of the companding scheme selected. Refer to
Figure 2 for a summary and comparison of the four PCM
data interface modes of this device.
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POWER–DOWN
There are two methods of putting this device into a low
power consumption mode, which makes the device nonfunc-
tional and consumes virtually no power. PDI is the power–
down input pin which, when taken low, powers down the
device. Another way to power the device down is to hold both
the FST and FSR pins low. When the chip is powered down,
the VAG, TG, RO+, RO–, PO+, PO–, and DT outputs are high
impedance. To return the chip to the power–up state, PDI
must be high and the FST frame sync pulse must be present.
Table 1. PCM Codes for Zero and Full Scale
Mu–Law
Level
L
l
+ Full Scale
+ Zero
– Zero
– Full Scale
Sign Bit
1
1
0
0
Chord Bits
000
111
111
000
Step Bits
0000
1111
1111
0000
Sign Bit
1
1
0
0
A–Law
Chord Bits
010
101
101
010
Step Bits
1010
0101
0101
1010
Table 2. PCM Codes for Digital mW
Mu–Law
Phase
Ph
π/8
3π/8
5π/8
7π/8
9π/8
11π/8
13π/8
15π/8
Sign Bit
0
0
0
0
1
1
1
1
Chord Bits
001
000
000
001
001
000
000
001
Step Bits
1110
1011
1011
1110
1110
1011
1011
1110
Sign Bit
0
0
0
0
1
1
1
1
A–Law
Chord Bits
011
010
010
011
011
010
010
011
Step Bits
0100
0001
0001
0100
0100
0001
0001
0100
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