CPM Electrical Characteristics
Table 21. SI Timing (continued)
Characteristic
All Frequencies
Num
Unit
Min
Max
74
75
76
77
78
L1CLKB edge to L1RSYNCB, L1TSYNCB, invalid (SYNC hold time)
L1RSYNCB, L1TSYNCB rise/fall time
35.00
—
—
ns
ns
15.00
—
L1RXDB valid to L1CLKB edge (L1RXDB setup time)
L1CLKB edge to L1RXDB invalid (L1RXDB hold time)
17.00
13.00
10.00
10.00
10.00
10.00
10.00
0.00
ns
—
ns
4
L1CLKB edge to L1ST1 and L1ST2 valid
45.00
45.00
45.00
55.00
55.00
42.00
ns
78A L1SYNCB valid to L1ST1 and L1ST2 valid
ns
79
80
L1CLKB edge to L1ST1 and L1ST2 invalid
L1CLKB edge to L1TXDB valid
ns
ns
80A L1TSYNCB valid to L1TXDB valid 4
ns
81
82
L1CLKB edge to L1TXDB high impedance
L1RCLKB, L1TCLKB frequency (DSC =1)
ns
—
16.00 or
SYNCCLK
/2
MHz
83
L1RCLKB, L1TCLKB width low (DSC =1)
P + 10
P + 10
—
—
—
ns
ns
83a L1RCLKB, L1TCLKB width high (DSC = 1)3
84
85
86
87
88
L1CLKB edge to L1CLKOB valid (DSC = 1)
L1RQB valid before falling edge of L1TSYNCB4
L1GRB setup time2
30.00
—
ns
1.00
42.00
42.00
—
L1TCLK
ns
—
L1GRB hold time
—
ns
L1CLKB edge to L1SYNCB valid (FSD = 00) CNT = 0000, BYT = 0,
DSC = 0)
0.00
ns
1 The ratio SyncCLK/L1RCLKB must be greater than 2.5/1.
2 These specs are valid for IDL mode only.
3 Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
4 These strobes and TxD on the first bit of the frame become valid after the L1CLKB edge or L1SYNCB, whichever
comes later.
MPC875/MPC870 Hardware Specifications, Rev. 3.0
51
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
FREESCALE [ Freescale ]
