CPM Electrical Characteristics
13.2 IDMA Controller AC Electrical Specifications
Table 18 provides the IDMA controller timings as shown in Figure 41 to Figure 44.
Table 18. IDMA Controller Timing
All
Frequencies
Num
Characteristic
Unit
Min
Max
40
41
42
43
44
45
46
DREQ setup time to clock high
DREQ hold time from clock high
7
TBD
—
—
—
12
12
20
15
—
ns
ns
ns
ns
ns
ns
ns
1
SDACK assertion delay from clock high
SDACK negation delay from clock low
—
SDACK negation delay from TA low
—
SDACK negation delay from clock high
—
TA assertion to falling edge of the clock setup time (applies to external TA)
7
1 Applies to high-to-low mode (EDM=1)
CLKO
(Output)
41
40
DREQ
(Input)
Figure 41. IDMA External Requests Timing Diagram
MPC875/MPC870 Hardware Specifications, Rev. 3.0
47
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
FREESCALE [ Freescale ]
