Electrical Design Considerations
•
To minimize temperature variation across the surface, the thermal resistance is measured from the
junction to the outside surface of the package (case) closest to the chip mounting area when that
surface has a proper heat sink.
•
•
To define a value approximately equal to a junction-to-board thermal resistance, the thermal
resistance is measured from the junction to where the leads are attached to the case.
If the temperature of the package case (T ) is determined by a thermocouple, the thermal resistance
T
is computed using the value obtained by the equation: (T – T )/P .
J
T
D
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the
first definition. From a practical standpoint, that value is also suitable for determining the junction
temperature from a case thermocouple reading in forced convection environments. In natural convection,
using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple
reading on the case of the package will estimate a junction temperature slightly hotter than actual
temperature. Hence, the new thermal metric, thermal characterization parameter or Ψ , has been defined
JT
to be (T – T )/P . This value gives a better estimate of the junction temperature in natural convection
J
T
D
when using the surface temperature of the package. Remember that surface temperature readings of
packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and
to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge
thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
5.2
Electrical Design Considerations
CAUTION
This device contains circuitry protecting against damage due to high static
voltage or electrical fields. However, normal precautions should be taken to
avoid exceeding maximum voltage ratings. Reliability of operation is
enhanced if unused inputs are tied to an appropriate logic voltage level (e.g.,
either GND or V ). The suggested value for a pull-up or pull-down resistor
CC
is 10 k ohm.
Use the following list of recommendations to assure correct DSP operation:
•
•
•
Provide a low-impedance path from the board power supply to each V pin on the DSP and from
the board ground to each GND pin.
CC
Use at least six 0.01–0.1 µF bypass capacitors positioned as close as possible to the four sides of
the package to connect the V power source to GND.
CC
Ensure that capacitor leads and associated printed circuit traces that connect to the chip V and
CC
GND pins are less than 1.2 cm (0.5 inch) per capacitor lead.
•
•
Use at least a four-layer PCB with two inner layers for V and GND.
CC
Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.
This recommendation particularly applies to the address and data buses as well as the IRQA,
IRQB, IRQD, and TA pins. Maximum PCB trace lengths on the order of 15 cm (6 inches) are
recommended.
DSP56367 Technical Data, Rev. 2.1
5-2
Freescale Semiconductor
FREESCALE [ Freescale ]
