欢迎访问ic37.com |
会员登录 免费注册
发布采购

DSPA56371 参数 Datasheet PDF下载

DSPA56371图片预览
型号: DSPA56371
PDF下载: 下载PDF文件 查看货源
内容描述: 该DSP56371是5.0伏兼容的输入和输出的高密度CMOS器件。 [The DSP56371 is a high density CMOS device with 5.0-volt compatible inputs and outputs.]
分类和应用:
文件页数/大小: 124 页 / 1701 K
品牌: FREESCALE [ Freescale ]
 浏览型号DSPA56371的Datasheet PDF文件第19页浏览型号DSPA56371的Datasheet PDF文件第20页浏览型号DSPA56371的Datasheet PDF文件第21页浏览型号DSPA56371的Datasheet PDF文件第22页浏览型号DSPA56371的Datasheet PDF文件第24页浏览型号DSPA56371的Datasheet PDF文件第25页浏览型号DSPA56371的Datasheet PDF文件第26页浏览型号DSPA56371的Datasheet PDF文件第27页  
Signal/Connection Descriptions  
Table 9. Enhanced Serial Audio Interface_1 Signals  
State during  
Signal Name  
Signal Type  
Signal Description  
Reset  
FSR_1  
Input or output  
GPIO  
Frame Sync for Receiver_1—This is the receiver frame sync  
disconnected input/output signal. In the asynchronous mode (SYN=0), the  
FSR_1 pin operates as the frame sync input or output used by  
all the enabled receivers. In the synchronous mode (SYN=1), it  
operates as either the serial flag 1 pin (TEBE=0), or as the  
transmitter external buffer enable control (TEBE=1, RFSD=1).  
When this pin is configured as serial flag pin, its direction is  
determined by the RFSD bit in the RCCR_1 register. When  
configured as the output flag OF1, this pin will reflect the value  
of the OF1 bit in the SAICR_1 register, and the data in the OF1  
bit will show up at the pin synchronized to the frame sync in  
normal mode or the slot in network mode. When configured as  
the input flag IF1, the data value at the pin will be stored in the  
IF1 bit in the SAISR register, synchronized by the frame sync in  
normal mode or the slot in network mode.  
PE1  
Input, output, or  
disconnected  
Port E1—When the ESAI_1 is configured as GPIO, this signal  
is individually programmable as input, output, or internally  
disconnected.  
The default state after reset is GPIO disconnected.  
Internal Pull down resistor.  
This input is 5 V tolerant.  
FST_1  
Input or output  
GPIO  
Frame Sync for Transmitter_1—This is the transmitter frame  
disconnected sync input/output signal. For synchronous mode, this signal is  
the frame sync for both transmitters and receivers. For  
asynchronous mode, FST_1 is the frame sync for the  
transmitters only. The direction is determined by the transmitter  
frame sync direction (TFSD) bit in the ESAI_1 transmit clock  
control register (TCCR_1).  
PE4  
Input, output, or  
disconnected  
Port E4—When the ESAI_1 is configured as GPIO, this signal  
is individually programmable as input, output, or internally  
disconnected.  
The default state after reset is GPIO disconnected.  
Internal Pull down resistor.  
This input is 5 V tolerant.  
Freescale Semiconductor  
DSP56371 Technical Data  
23  
 复制成功!