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DSPA56371 参数 Datasheet PDF下载

DSPA56371图片预览
型号: DSPA56371
PDF下载: 下载PDF文件 查看货源
内容描述: 该DSP56371是5.0伏兼容的输入和输出的高密度CMOS器件。 [The DSP56371 is a high density CMOS device with 5.0-volt compatible inputs and outputs.]
分类和应用:
文件页数/大小: 124 页 / 1701 K
品牌: FREESCALE [ Freescale ]
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Signal/Connection Descriptions  
3.9  
Enhanced Serial Audio Interface_1  
Table 9. Enhanced Serial Audio Interface_1 Signals  
State during  
Signal Name  
Signal Type  
Signal Description  
Reset  
HCKR_1  
Input or output  
GPIO  
High Frequency Clock for Receiver—When programmed as  
disconnected an input, this signal provides a high frequency clock source for  
the ESAI_1 receiver as an alternate to the DSP core clock.  
When programmed as an output, this signal can serve as a  
high-frequency sample clock (e.g., for external digital to analog  
converters [DACs]) or as an additional system clock.  
PE2  
Input, output, or  
disconnected  
Port E2—When the ESAI_1 is configured as GPIO, this signal  
is individually programmable as input, output, or internally  
disconnected.  
The default state after reset is GPIO disconnected.  
Internal Pull down resistor.  
This input is 5 V tolerant.  
HCKT_1  
Input or output  
GPIO  
High Frequency Clock for Transmitter—When programmed  
disconnected as an input, this signal provides a high frequency clock source  
for the ESAI_1 transmitter as an alternate to the DSP core  
clock. When programmed as an output, this signal can serve as  
a high frequency sample clock (e.g., for external DACs) or as an  
additional system clock.  
PE5  
Input, output, or  
disconnected  
Port E5—When the ESAI_1 is configured as GPIO, this signal  
is individually programmable as input, output, or internally  
disconnected.  
The default state after reset is GPIO disconnected.  
Internal Pull down resistor.  
This input is 5 V tolerant.  
22  
DSP56371 Technical Data  
Freescale Semiconductor  
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