Packaging
3.3 MAP-BGA Package Description
Top and bottom views of the MAP-BGA package are shown in Figure 3-4 and Figure 3-5 with their pin-outs.
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
NC
HAD15 HCLK HPAR HPERR HIRDY HAD16 HAD17 HAD20 HAD23 HAD24 HAD27 HAD30
NC
HDEV
SEL
NC
NC
HAD14 HGNT HRST HSERR
HIDSEL HC2 HAD19 HAD22 HAD25 HAD29 HAD31
H
NC
NC
C
D
E
F
HAD8 HAD11 HAD12 HAD13 HC1
HAD5 HAD7 HAD9 HAD10 VCC
HREQ HLOCK
HAD18 HAD21 HC3 HAD26 MODD
NC
NC
NC
D23
D21
D17
FRAME
PVCL HSTOP HTRDY VCC
VCC
VCC HAD28 MODC
NC
MODB
HAD2 HAD4 HAD6
HAD1 HAD0 HAD3
HC0
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
D18
MODA D22
VCC
GND
GND
GND
GND
GND
GND
VCC
D19
D20
G
H
TI01
RXD
TI02
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
D12
D11
D15
D9
D16
D13
D14
D8
SCLK HINTA TI00
VCC
VCC
VCC
J
SC11 SC12
TXD
SC10
VCC
GND
GND
GND
GND
GND
GND
VCC
VCC
D5
D10
D7
K
L
STD1 SCK1 SCK0 SRD0
SRD1 STD0 SC02 SC01
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
D3
D0
D6
D2
D4
D1
VCC
VCC
VCC
M
N
P
R
T
SC00
TCK
TRST
NC
DE
TDI
BS
TDO
NC
TMS
BL
VCC
TA
VCC
VCC
VCC
BG
VCC
VCC
AA3
VCC
A1
VCC
A2
VCC
VCC
A8
VCC
VCC
A12
A9
A19
A16
NC
A21
A17
A15
A14
A13
A22
A20
NC
NC
NC
A23
NC
VCC
CLK
OUT
AA0
AA1
PINIT GNDP
EXTAL
A5
A18
NC
NC
NC
CAS
VCCP
BB
AA2
BR
XTAL BCLK
A3
A6
A11
A10
BCLK RESET PCAP GNDP1
WR
RD
A0
A4
A7
Figure 3-4. DSP56301 Molded Array Process-Ball Grid Array (MAP-BGA), Top View
DSP56301 Technical Data, Rev. 10
3-12
Freescale Semiconductor
FREESCALE [ Freescale ]
