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DSP56301VF100 参数 Datasheet PDF下载

DSP56301VF100图片预览
型号: DSP56301VF100
PDF下载: 下载PDF文件 查看货源
内容描述: 24位数字信号处理器 [24-Bit Digital Signal Processor]
分类和应用: 外围集成电路数字信号处理器时钟
文件页数/大小: 124 页 / 2296 K
品牌: FREESCALE [ Freescale ]
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Signals/Connections  
Signal Name  
Table 1-14. Serial Communication Interface (SCI) (Continued)  
State During  
Type  
Signal Description  
Reset  
SCLK  
PE2  
Input/Output  
Input  
Serial Clock  
Provides the input or output clock used by the transmitter and/or the receiver.  
Input or Output  
Port E 2  
The default configuration following reset is GPIO. For PE2, signal direction is  
controlled through the SCI PRR. The signal can be configured as an SCI  
signal SCLK through the SCI PCR.  
This input is 5 V tolerant.  
1.11 Timers  
The DSP56301 has three identical and independent timers. Each can use internal or external clocking, interrupt the  
DSP56301 after a specified number of events (clocks), or signal an external device after counting a specific number  
of internal events.  
Table 1-15. Triple Timer Signals  
State During  
Signal Name  
Type  
Signal Description  
Reset  
TIO0  
Input or Output  
Input  
Input  
Input  
Timer 0 Schmitt-Trigger Input/Output  
As an external event counter or in Measurement mode, TIO0 is input. In  
Watchdog, Timer, or Pulse Modulation mode, TIO0 is output.  
The default mode after reset is GPIO input. This can be changed to output or  
configured as a Timer Input/Output through the Timer 0 Control/Status  
Register (TCSR0).  
This input is 5 V tolerant.  
TIO1  
Input or Output  
Timer 1 Schmitt-Trigger Input/Output  
As an external event counter or in Measurement mode, TIO1 is input. In  
Watchdog, Timer, or Pulse Modulation mode, TIO1 is output.  
The default mode after reset is GPIO input. This can be changed to output or  
configured as a Timer Input/Output through the Timer 1 Control/Status  
Register (TCSR1).  
This input is 5 V tolerant.  
TIO2  
Input or Output  
Timer 2 Schmitt-Trigger Input/Output  
As an external event counter or in Measurement mode, TIO2 is input. In  
Watchdog, Timer, or Pulse Modulation mode, TIO2 is output.  
The default mode after reset is GPIO input. This can be changed to output or  
configured as a Timer Input/Output through the Timer 2 Control/Status  
Register (TCSR2).  
This input is 5 V tolerant.  
DSP56301 Technical Data, Rev. 10  
1-20  
Freescale Semiconductor  
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