Freescale Semiconductor, Inc.
0–2 CLOCKS*
S0
S2
S4
S0
S1 S2
S4
S0
S2
CLKOUT
A31–A4
A3–A1
A0
INTERRUPT LEVEL
FC3–FC0
CPU SPACE
1 BYTE
SIZ0
SIZ1
R/W
AS
DS
VECTOR FROM 16-BIT PORT
VECTOR FROM 8-BIT PORT
DSACKx
D7–D0
D15–D8
IRQ7–IRQ1
IACK7–IACK1
READ
CYCLE
WRITE
STACK
INTERNAL
ARBITRATION
IACK CYCLE
*Internal Arbitration may take between 0–2 clock cycles.
Figure 3-15. Interrupt Acknowledge Cycle Timing
3.4.4.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE. When the interrupting
device cannot supply a vector number, it requests an automatically generated vector
(autovector). Instead of placing a vector number on the data bus and asserting DSACK≈,
the device asserts AVEC to terminate the cycle. If the DSACK≈ signals are asserted
during an interrupt acknowledge cycle terminated by AVEC, the DSACK≈ signals and
MOTOROLA
MC68340 USER’S MANUAL
3- 29
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