Freescale Semiconductor, Inc.
The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in
3.3.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences
are as follows:
1. FC3–FC0 are set to $7 (FC3/FC2/FC1/FC0 = 0111) for CPU address space.
2. A3, A2, and A1 are set to the interrupt request level, and the IACK≈ strobe
corresponding to the current interrupt level is asserted. (Either the function codes
and address signals or the IACK≈ strobes can be monitored to determine that an
interrupt acknowledge cycle is in progress and the current interrupt level.)
3. The CPU32 space type field (A19–A16) is set to $F (interrupt acknowledge).
4. Other address signals (A31–A20, A15–A4, and A0) are set to one.
5. The SIZ0/SIZ1 and R/W signals are driven to indicate a single-byte read cycle.
The responding device places the vector number on the least significant byte
of its data port (for an 8-bit port, the vector number must be on D15–D8; for a
16-bit port, the vector must be on D7–D0) during the interrupt acknowledge cycle.
The cycle is then terminated normally with DSACK≈.
Figure 3-14 is a flowchart of the interrupt acknowledge cycle; Figure 3-15 shows the
timing for an interrupt acknowledge cycle terminated with DSACK≈.
INTERRUPTING DEVICE
REQUEST INTERRUPT
MC68340
GRANT INTERRUPT
1. SYNCHRONIZE IRQ7–IRQ1
2. COMPARE IRQ1–IRQ7 TO MASK LEVEL AND
WAIT FOR INSTRUCTION TO COMPLETE
3. PLACE INTERRUPT LEVEL ON A3–A1;
TYPE FIELD (A19–A16) = $F
4. SET R/W TO READ
5. SET FC3–FC0 TO 0111
6. DRIVE SIZE PINS TO INDICATE A ONE-BYTE
TRANSFER
7. ASSERT AS AND DS
8. ASSERT THE CORRESPONDING IACKx STROBE.
PROVIDE VECTOR NUMBER
1. PLACE VECTOR NUMBER ON LEAST
SIGNIFICANT BYTE OF DATA BUS
2. ASSERT DSACKx (OR AVEC IF NO VECTOR
NUMBER)
ACQUIRE VECTOR NUMBER
1. LATCH VECTOR NUMBER
2. NEGATE DS AND AS
RELEASE
1. NEGATE DSACKx
START NEXT CYCLE
Figure 3-14. Interrupt Acknowledge Cycle Flowchart
3- 28
MC68340 USER’S MANUAL
MOTOROLA
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