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Commands are received over a dedicated, high-speed, full-duplex serial interface.
Commands allow the manual reading or writing of CPU32 registers, reading or writing of
external memory locations, and diversion to user-specified patch code. This background
debug mode permits a much simpler emulation environment while leaving the processor
chip in the target system, running its own debugging operations.
1.3 ON-CHIP PERIPHERALS
To improve total system throughput and reduce part count, board size, and cost of system
implementation, the M68300 family integrates on-chip, intelligent peripheral modules and
typical glue logic. These functions on the MC68340 include the SIM40, a DMA controller,
a serial module, and two timers.
The processor communicates with these modules over the on-chip intermodule bus (IMB).
This backbone of the chip is similar to traditional external buses with address, data, clock,
interrupt, arbitration, and handshake signals. Because bus masters (like the CPU32 and
DMA), peripherals, and the SIM40 are all on the chip, the IMB ensures that
communication between these modules is fully synchronized and that arbitration and
interrupts can be handled in parallel with data transfers, greatly improving system
performance. Internal accesses across the IMB may be monitored from outside of the
chip, if desired.
Each module operates independently. No direct connections between peripheral modules
are made inside the chip; however, external connections could, for instance, link a serial
output to a DMA control line. Modules and their registers are accessed in the memory
map of the CPU32 (and DMA) for easy access by general M68000 instructions and are
relocatable. Each module may be assigned its own interrupt level, response vector, and
arbitration priority. Since each module is a self-contained design and adheres to the IMB
interface specifications, the modules may appear on other M68300 family products,
retaining the investment in the software drivers for the module.
1.3.1 System Integration Module
The MC68340 SIM40 provides the external bus interface for both the CPU32 and the
DMA. It also eliminates much of the glue logic that typically supports the microprocessor
and its interface with the peripheral and memory system. The SIM40 provides
programmable circuits to perform address decoding and chip selects, wait-state insertion,
interrupt handling, clock generation, bus arbitration, watchdog timing, discrete I/O, and
power-on reset timing. A boundary scan test capability is also provided.
1.3.1.1 EXTERNAL BUS INTERFACE. The external bus interface (EBI) handles the
transfer of information between the internal CPU32 or DMA controller and memory,
peripherals, or other processing elements in the external address space. Based on the
MC68030 bus, the external bus provides up to 32 address lines and 16 data lines.
Address extensions identify each bus cycle as CPU32 or DMA initiated, supervisor or user
privilege level, and instruction or data access. The data bus allows dynamic sizing for 8- or
16-bit bus accesses (plus 32 bits for DMA). Synchronous transfers from the CPU32 or the
DMA can be made in as little as two clock cycles. Asynchronous transfers allow the
MOTOROLA
MC68340 USER’S MANUAL
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