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AN1063D 参数 Datasheet PDF下载

AN1063D图片预览
型号: AN1063D
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的处理器与DMA USERA ????手册 [Integrated Processor with DMA User’s Manual]
分类和应用:
文件页数/大小: 441 页 / 2488 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
5.5.3.1.3 Type III—Faults During MOVEM Operand Transfer. Bus faults that occur as a  
result of MOVEM operand transfer are classified as type III faults. MOVEM instruction  
prefetch faults are type II faults.  
Type III faults cause an immediate exception that aborts the current instruction. None of  
the registers altered during execution of the faulted instruction are restored prior to  
execution of the fault handler. This includes any register predecremented as a result of the  
effective address calculation or any register overwritten during instruction execution. Since  
postincremented registers are not updated until the end of an instruction, the register  
retains its pre-instruction value unless overwritten by operand movement.  
The SSW for faults in this category contains the following bit pattern:  
15  
0
14  
1
13  
0
12  
11  
10  
9
8
0
7
6
5
4
3
2
0
TR  
B1  
B0  
RR  
IN  
RW  
LG  
SIZ  
FUNC  
MV is set, indicating that MOVEM should be continued from the point where the fault  
occurred upon return from the exception handler. TR, B1, and B0 are set if a  
corresponding exception is pending when the bus error exception is taken. IN is set if a  
bus fault occurs while prefetching an opcode or an extension word during instruction  
restart. RW, LG, SIZ, and FUNC all reflect the type of bus cycle that caused the fault. All  
write faults have the RR bit set to indicate that the write should be rerun upon return from  
the exception handler.  
The remainder of the stack frame contains sufficient information to continue MOVEM with  
operand transfer following a faulted transfer. The address of the next operand to be  
transferred, incremented or decremented by operand size, is stored in the faulted address  
location ($08). The stacked transfer counter is set to 16 minus the number of transfers  
attempted (including the faulted cycle). Refer to Figure 5-12 for the stacking format.  
5.5.3.1.4 Type IV—Faults During Exception Processing. The fourth type of fault occurs  
during exception processing. If this exception is a second address or bus error, the  
machine halts in the double bus fault condition. However, if the exception is one that  
causes a four- or six-word stack frame to be written, a bus cycle fault frame is written  
below the faulted exception stack frame.  
The SSW for a fault within an exception contains the following bit pattern:  
15  
1
14  
0
13  
0
12  
11  
10  
9
0
8
0
7
0
6
1
5
4
3
2
0
TR  
B1  
B0  
LG  
SIZ  
FUNC  
TR, B1, and B0 are set if a corresponding exception is pending when the bus error  
exception is taken.  
The contents of the faulted exception stack frame are included in the bus fault stack  
frame. The pre-exception SR and the format/vector word of the faulted frame are stacked.  
The type of exception can be determined from the format/vector word. If the faulted  
exception stack frame contains six words, the PC of the instruction that caused the initial  
5- 56  
MC68340 USER’S MANUAL  
MOTOROLA  
For More Information On This Product,  
Go to: www.freescale.com  
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