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AN1063D 参数 Datasheet PDF下载

AN1063D图片预览
型号: AN1063D
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的处理器与DMA USERA ????手册 [Integrated Processor with DMA User’s Manual]
分类和应用:
文件页数/大小: 441 页 / 2488 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Read and write bus cycles are distinguished by the RW bit. Read bus cycles will set this  
bit, and write bus cycles will clear it. RW is reloaded into the bus controller if the RR bit  
is set during unstacking.  
0 = Faulted cycle was an operand write  
1 = Faulted cycle was a prefetch or operand read  
The LG bit indicates an original operand size of long word. LG is cleared if the original  
operand was a byte or word—SIZ will indicate original (and remaining) size. LG is set if  
the original was a long word—SIZ will indicate the remaining size at the time of fault. LG  
is ignored during unstacking.  
0 = Original operand size was byte or word  
1 = Original operand size was long word  
The SSW SIZ field shows operand size remaining when a fault was detected. This field  
does not indicate the initial size of the operand, nor does it necessarily indicate the  
proper status of a dynamically sized bus cycle. Dynamic sizing occurs on the external  
bus and is transparent to the CPU. Byte size is shown only when the original operand  
was a byte. The field is reloaded into the bus controller if the RR bit is set during  
unstacking. The SIZ field is encoded as follows:  
00—Long word  
01—Byte  
10—Word  
11—Unused, reserved  
The function code for the faulted cycle is stacked in the FUNC field of the SSW, which is  
a copy of FC2–FC0 for the faulted bus cycle. This field is reloaded into the bus  
controller if the RR bit is set during unstacking. All unused bits are stacked as zeros and  
are ignored during unstacking. Further discussion of the SSW is included in 5.5.3.1  
Types of Faults.  
5.5.3.1 TYPES OF FAULTS. An efficient implementation of instruction restart dictates that  
faults on some bus cycles be treated differently than faults on other bus cycles. The  
CPU32 defines four fault types: released write faults, faults during exception processing,  
faults during MOVEM operand transfer, and faults on any other bus cycle.  
5.5.3.1.1 Type I—Released Write Faults. CPU32 instruction pipelining can cause a final  
instruction write to overlap the execution of a following instruction. A write that is  
overlapped is called a released write. A released write fault occurs when a bus error or  
some other fault occurs on the released write.  
Released write faults are taken at the next instruction boundary. The stacked PC is that of  
the next unexecuted instruction. If a subsequent instruction attempts an operand access  
while a released write fault is pending, the instruction is aborted and the write fault is  
acknowledged. This action prevents stale data from being used by the instruction.  
5- 54  
MC68340 USER’S MANUAL  
MOTOROLA  
For More Information On This Product,  
Go to: www.freescale.com  
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