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5.5.2.10 TRACING. To aid in program development, M68000 processors include a facility
to allow tracing of instruction execution. CPU32 tracing also has the ability to trap on
changes in program flow. In trace mode, a trace exception is generated after each
instruction executes, allowing a debugging program to monitor the execution of a program
under test. The T1 and T0 bits in the supervisor portion of the SR are used to control
tracing.
When T1–T0 = 00, tracing is disabled, and instruction execution proceeds normally (see
Table 5-18).
Table 5-18. Tracing Control
T1
T0
Tracing Function
No tracing
0
0
0
1
1
1
0
1
Trace on change of flow
Trace on instruction execution
Undefined; reserved
When T1–T0 = 01 at the beginning of instruction execution, a trace exception will be
generated if the PC changes sequence during execution. All branches, jumps, subroutine
calls, returns, and SR manipulations can be traced in this way. No exception occurs if a
branch is not taken.
When T1–T0 = 10 at the beginning of instruction execution, a trace exception will be
generated when execution is complete. If the instruction is not executed, either because
an interrupt is taken or because the instruction is illegal, unimplemented, or privileged, an
exception is not generated.
At the present time, T1–T0 = 11 is an undefined condition. It is reserved by Motorola for
future use.
Exception processing for trace starts at the end of normal processing for the traced
instruction and before the start of the next instruction. Exception processing follows the
regular sequence; tracing is disabled so that the trace exception itself is not traced. A
vector number is generated to reference the trace exception vector. The address of the
instruction that caused the trace exception, the trace exception vector offset, the current
PC, and a copy of the SR are saved on the supervisor stack. The saved value of the PC is
the address of the next instruction to be executed.
A trace exception can be viewed as an extension to the function of any instruction. If a
trace exception is generated by an instruction, the execution of that instruction is not
complete until the trace exception processing associated with it is also complete.
If an instruction is aborted by a bus error or address error exception, trace exception
processing is deferred until the suspended instruction is restarted and completed
normally. An RTE from a bus error or address error will not be traced because of the
possibility of continuing the instruction from the fault.
MOTOROLA
MC68340 USER’S MANUAL
5- 49
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