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5.5.2 Processing of Specific Exceptions
The following paragraphs provide details concerning sources of specific exceptions, how
each arises, and how each is processed.
5.5.2.1 RESET. Assertion of RESET by external hardware or assertion of the internal
RESET signal by an internal module causes a reset exception. The reset exception has
the highest priority of any exception. Reset is used for system initialization and for
recovery from catastrophic failure. The reset exception aborts any processing in progress
when it is recognized, and that processing cannot be recovered. Reset performs the
following operations:
1. Clears T0 and T1 in the SR to disable tracing
2. Sets the S-bit in the SR to establish supervisor privilege
3. Sets the interrupt priority mask to the highest priority level (%111)
4. Initializes the VBR to zero ($00000000)
5. Generates a vector number to reference the reset exception vector
6. Loads the first long word of the vector into the interrupt SP
7. Loads the second long word of the vector into the PC
8. Fetches and initiates decode of the first instruction to be executed
Figure 5-11 is a flowchart of the reset exception
After initial instruction prefetches, normal program execution begins at the address in the
PC. The reset exception does not save the value of either the PC or the SR.
If a bus error or address error occurs during reset exception processing sequence, a
double bus fault occurs, the processor halts, and the HALT signal is asserted to indicate
the halted condition.
Execution of the RESET instruction does not cause a reset exception nor does it affect
any internal CPU register. The SIM40 registers and the MCR in each internal peripheral
module (DMA, timers, and serial modules) are not affected. All other internal peripheral
module registers are reset the same as for a hardware reset. The external devices
connected to the RESET signal are reset at the completion of the RESET instruction.
MOTOROLA
MC68340 USER’S MANUAL
5- 43
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