Freescale Semiconductor, Inc.
Table 5-2. Instruction Set Summary (Concluded)
Opcode
Operation
Syntax
1
1
ROXL,ROXR
Destination Rotated with X by count
Destination ROXd Rx,Dy
ROXd # data ,Dy
1
ROXd ea
RTD
RTE
(SP)
PC; SP + 4 + d
SP
SP; (SP)
RTD # displacement
If supervisor state
the (SP)
SP + 4
RTE
PC;
SR; SP + 2
SP;
restore state and deallocate stack according to (SP)
else TRAP
RTR
(SP)
(SP)
CCR; SP + 2
PC; SP + 4
SP;
SP
RTR
RTS
RTS
(SP)
PC; SP + 4
SP
SBCD
Destination – Source – X
Destination
SBCD Dx,Dy
SBCD –(Ax),–(Ay)
10
10
Scc
STOP
SUB
If Condition True
Scc ea
then 1s
else 0s
Destination
Destination
If supervisor state
then Immediate Data
else TRAP
STOP # data
SR; STOP
Destination – Source
Destination
Destination
SUB ea ,Dn
SUB Dn, ea
SUBA
SUBI
Destination – Source
SUBA ea ,An
Destination – Immediate Data
Destination – Immediate Data
Destination
Destination
SUBI # data , ea
SUBQ # data , ea
SUBQ
SUBX
Destination – Source – X
Destination
SUBX Dx,Dy
SUBX –(Ax),–(Ay)
SWAP
TAS
Register [31:16]
Register [15:0]
Condition Codes;
SWAP Dn
TAS ea
Destination Tested
1
bit 7 of Destination
TBLS
TBLSN
TBLU
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n))
TBLS. size ea , Dx
TBLS. size Dym:Dyn, Dx
*
Dx[7:0]} / 256
Dx
ENTRY(n) × 256 + {(ENTRY(n + 1) – ENTRY(n))
TBLSN. size ea ,Dx
TBLSN. size Dym:Dyn, Dx
*
Dx [7:0]}
Dx
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n))
TBLU. size ea ,Dx
TBLU. size Dym:Dyn, Dx
*
Dx[7:0]} / 256
Dx
TBLUN
TRAP
ENTRY(n) • 256 + {(ENTRY(n + 1) – ENTRY(n)) •
TBLUN. size ea ,Dx
TBLUN. size Dym:Dyn,Dx
Dx[7:0]}
Dx
SSP – 2
SSP – 4
SSP; Format/Offset
(SSP);
TRAP # vector
SSP; PC
(SSP); SSP – 2
SSP;
SR
(SSP); Vector Address
PC
TRAPcc
If cc then TRAP
TRAPcc
TRAPcc.W # data
TRAPcc.L # data
TRAPV
TST
If V then TRAP
TRAPV
TST ea
UNLK An
Destination Tested
Condition Codes
UNLK
An
SP; (SP)
An; SP + 4
SP
NOTE 1: d is direction, L or R.
MOTOROLA
MC68340 USER’S MANUAL
5- 19
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