Freescale Semiconductor, Inc.
Table 5-2. Instruction Set Summary
Opcode
Operation
Syntax
ABCD
Source + Destination + X
Destination
Destination
Destination
ABCD Dy,Dx
ABCD –(Ay),–(Ax)
10
10
ADD
Source + Destination
ADD ea ,Dn
ADD Dn, ea
ADDA
ADDI
Source + Destination
ADDA ea ,An
Immediate Data + Destination
Immediate Data + Destination
Source + Destination + X
Destination
Destination
ADDI # data , ea
ADDQ # data , ea
ADDQ
ADDX
Destination
Destination
ADDX Dy,Dx
ADDX –(Ay),–(Ax)
AND
Source Λ Destination
AND ea ,Dn
AND Dn, ea
ANDI
Immediate Data Λ Destination
Destination
ANDI # data , ea
ANDI # data ,CCR
ANDI # data ,SR
ANDI to CCR
ANDI to SR
Source Λ CCR
CCR
If supervisor state
the Source Λ SR
else TRAP
SR
ASL,ASR
Destination Shifted by count
Destination
PC
ASd Dx,Dy
ASd # data ,Dy
ASd ea
Bcc
If (condition true) then PC + d
~( number of Destination) Z;
Bcc label
BCHG
BCHG Dn, ea
~( number of Destination)
Destination
bit number of
BCHG # data , ea
BCLR
BGND
~( number of Destination) Z;
bit number of Destination
BCLR Dn, ea
BCLR # data , ea
0
If (background mode enabled) then
enter background mode
BGND
else Format/Vector offset
–(SSP)
PC
SR
(Vector)
–(SSP)
–(SSP)
PC
BKPT
Run breakpoint acknowledge cycle;
TRAP as illegal instruction
BKPT # data
BRA label
BRA
PC + d PC
BSET
~( number of Destination) Z;
BSET Dn, ea
BSET # data , ea
1
bit number of Destination
BSR
SP – 4 SP; PC (SP); PC + d
PC
BSR label
BTST
– ( number of Destination) Z;
BTST Dn, ea
BTST # data , ea
CHK
If Dn < 0 or Dn > Source then TRAP
CHK ea ,Dn
CHK2 ea ,Rn
CHK2
If Rn < lower bound or
If Rn > upper bound
then TRAP
CLR
CMP
0
Destination
CLR ea
Destination — Source
Destination — Source
cc
CMP ea ,Dn
CMPA ea ,An
CMPI # data , ea
CMPM (Ay)+,(Ax)+
CMPA
CMPI
CMPM
Destination — Immediate Data
Destination — Source cc
5- 16
MC68340 USER’S MANUAL
MOTOROLA
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