Freescale Semiconductor, Inc.
Registers
Address
$031B
$031C
$031D
$031E
$031F
Bit 7
6
5
4
3
2
1
Bit 0
AC0
AM0
AM0
AM0
AM0
Name
AC7
AM7
AM7
AM7
AM7
AC6
AM6
AM6
AM6
AM6
AC5
AM5
AM5
AM5
AM5
AC4
AM4
AM4
AM4
AM4
AC3
AM3
AM3
AM3
AM3
AC2
AM2
AM2
AM2
AM2
AC1
AM1
AM1
AM1
AM1
C1IDAR7
C1IDMR4
C1IDMR5
C1IDMR6
C1IDMR7
$0320–
$033C
Unimplemented(4)
Reserved
$033D
$033E
0
0
0
0
0
0
PUPCAN RDPCAN PCTLCAN1
PCAN7
PCAN6
PCAN5
PCAN4
PCAN3
PCAN2
TxCAN
0
RxCAN PORTCAN1
$033F DDCAN7 DDCAN6 DDCAN5 DDCAN4 DDCAN3 DDCAN2
0
DDRCAN1
$0340–
FOREGROUND RECEIVE BUFFER 1
$034F
RxFG1
$0350–
TRANSMIT BUFFER 10
$035F
Tx10
Tx11
$0360–
TRANSMIT BUFFER 11
$036F
$0370–
TRANSMIT BUFFER 12
$037F
Tx12
$0380-
Unimplemented(4)
$03FF
Reserved
= Reserved or unimplemented bits.
Table 4-1. Register Map (Sheet 10 of 10)
1. Port A, port B and data direction registers DDRA, DDRB are not in map in expanded and peripheral modes.
2. Port E and DDRE not in the map in peripheral and expanded modes with EME set.
3. Registers also not in map in peripheral mode.
4. Data read at these locations is undefined.
5. Port K and DDRK not in the map in peripheral and expanded modes with EMK set.
Technical Data
MC68HC912DG128 — Rev 3.0
Registers
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