Freescale Semiconductor, Inc.
Technical Data — MC68HC912DG128
Section 3. Pinout and Signal Descriptions
3.1 Contents
3.2
3.3
3.4
3.5
Pin Assignments in 112-pin QFP . . . . . . . . . . . . . . . . . . . . . . .37
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.2 Pin Assignments in 112-pin QFP
The MC68HC912DG128 is available in a 112-pin thin quad flat pack
(TQFP). Most pins perform two or more functions, as described in the
Signal Descriptions. Figure 3-2 shows pin assignments. In expanded
narrow modes the lower byte data is multiplexed with higher byte data
through pins 57-64.
MC68HC912DG128 — Rev 3.0
Technical Data
Pinout and Signal Descriptions
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