Freescale Semiconductor, Inc.
Technical Data — MC68HC912DG128
Section 2. Central Processing Unit
2.1 Contents
2.2
2.3
2.4
2.5
2.6
2.7
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.2 Introduction
The CPU12 is a high-speed, 16-bit processing unit. It has full 16-bit data
paths and wider internal registers (up to 20 bits) for high-speed extended
math instructions. The instruction set is a proper superset of the
M68HC11instruction set. The CPU12 allows instructions with odd byte
counts, including many single-byte instructions. This provides efficient
use of ROM space. An instruction queue buffers program information so
the CPU always has immediate access to at least three bytes of machine
code at the start of every instruction. The CPU12 also offers an
extensive set of indexed addressing capabilities.
2.3 Programming Model
CPU12 registers are an integral part of the CPU and are not addressed
as if they were memory locations.
MC68HC912DG128 — Rev 3.0
Technical Data
Central Processing Unit
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