Freescale Semiconductor, Inc.
Pulse Width Modulator
Introduction
CLOCK SOURCE
(ECLK or Scaled ECLK)
CENTR = 1
FROM PORT P
DATA REGISTER
RESET
PWCNTx
GATE
(CLOCK EDGE SYNC)
(DUTY CYCLE)
N
8-BIT COMPARE =
PWDTYx
O
D/
T
U
Q
Q
MUX
MUX
(PERIOD)
8-BIT COMPARE =
PWPERx
TO PIN
DRIVER
PPOLx
PWENx
SYNC
PPOL = 1
PPOL = 0
(PWPER − PWDTY) × 2
PWDTY
PWDTY
PWPER × 2
Figure 12-2. Block Diagram of PWM Center-Aligned Output Channel
MC68HC912DG128 — Rev 3.0
Technical Data
Pulse Width Modulator
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