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68HC912DG128CPV8 参数 Datasheet PDF下载

68HC912DG128CPV8图片预览
型号: 68HC912DG128CPV8
PDF下载: 下载PDF文件 查看货源
内容描述: M68HC12微控制器 [M68HC12 Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 452 页 / 3509 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Flash Memory  
7.7 Flash EEPROM Registers  
Each 32K byte Flash EEPROM module has a set of registers. The  
register space $00F4-$00F7 is in a register space window of four pages.  
Each register page of four bytes maps the register space for each Flash  
module and each page is selected by the PPAGE register. See  
Operating Modes.  
FEELCK — Flash EEPROM Lock Control Register  
$00F4  
Bit 7  
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
Bit 0  
LOCK  
0
0
0
RESET:  
In normal modes the LOCK bit can only be written once after reset.  
LOCK — Lock Register Bit  
0 = Enable write to FEEMCR register  
1 = Disable write to FEEMCR register  
FEEMCR — Flash EEPROM Module Configuration Register  
$00F5  
Bit 7  
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
Bit 0  
BOOTP  
1
0
0
RESET:  
This register controls the operation of the Flash EEPROM array.  
BOOTP cannot be changed when the LOCK control bit in the  
FEELCK register is set or if ENPE in the FEECTL register is set.  
BOOTP — Boot Protect  
The boot blocks are located at $E000–$FFFF and $A000–$BFFF for  
odd program pages for each Flash EEPROM module. Since boot  
programs must be available at all times, the only useful boot block is  
at $E000–$FFFF location. All paged boot blocks can be used as  
protected program space if desired.  
0 = Enable erase and program of 8K byte boot block  
1 = Disable erase and program of 8K byte boot block  
Technical Data  
MC68HC912DG128 — Rev 3.0  
Flash Memory  
For More Information On This Product,  
Go to: www.freescale.com