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68HC912DG128CPV8 参数 Datasheet PDF下载

68HC912DG128CPV8图片预览
型号: 68HC912DG128CPV8
PDF下载: 下载PDF文件 查看货源
内容描述: M68HC12微控制器 [M68HC12 Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 452 页 / 3509 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Flash Memory  
Flash EEPROM Control Block  
always be within the specification as defined in Table 19-10 in Electrical  
Specifications. Programming is by byte or aligned word. The Flash  
EEPROM module supports bulk erase only.  
The Flash EEPROM module has hardware interlocks which protect  
stored data from accidental corruption. An erase- and program-  
protected 8-Kbyte block for boot routines is located at the top of each 32-  
Kbyte array. Since boot programs must be available at all times, the only  
useful boot block is at $E000–$FFFF location. All paged boot blocks can  
be used as protected program space if desired.  
7.5 Flash EEPROM Control Block  
A 4-byte register block for each module controls the Flash EEPROM  
module operation. Configuration information is specified and  
programmed independently from the contents of the Flash EEPROM  
array. At reset, the 4-byte register section starts at address $00F4 and  
points to the 00FEE32K register block.  
7.6 Flash EEPROM Arrays  
After reset, a fixed 32K Flash EEPROM array, 11FEE32K, is located  
from addresses $4000 to $7FFF and from $C000 to $FFFF. The other  
three 32K Flash EEPROM arrays 00FEE32K, 01FEE32K and  
10FEE32K, are mapped through a 16K byte program page window  
located from addresses $8000 to $BFFF. The page window has eight  
16K byte pages. The last two pages also map the physical location of the  
fixed 32K Flash EEPROM array 11FEE32K. In expanded modes, the  
Flash EEPROM arrays are turned off. See Operating Modes.  
MC68HC912DG128 — Rev 3.0  
Technical Data  
Flash Memory  
For More Information On This Product,  
Go to: www.freescale.com