Freescale Semiconductor, Inc.
List of Figures
Figure
Title
Page
6-12 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
6-13 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . .95
6-14 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . .95
6-15 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
6-16 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . . .96
6-17 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . .97
6-18 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . .98
6-19 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . .99
7-1
7-2
7-3
7-4
Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .102
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Break Status and Control Register (BSCR) . . . . . . . . . . . . . .105
Break Address Registers (BRKH and BRKL) . . . . . . . . . . . . .106
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
ICG Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .110
Internal Clock Generator Block Diagram . . . . . . . . . . . . . . . .111
External Clock Generator Block Diagram. . . . . . . . . . . . . . . .114
Clock Monitor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .117
Clock Selection Circuit Block Diagram . . . . . . . . . . . . . . . . . .120
Synchronizing Clock Switcher Circuit Diagram. . . . . . . . . . . .121
Code Example for Switching Clock Sources . . . . . . . . . . . . .123
Code Example for Enabling the Clock Monitor. . . . . . . . . . . .124
Code Example for Writing DDIV and DSTG . . . . . . . . . . . . . .133
8-10 ICG I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .137
8-11 ICG Control Register (ICGCR) . . . . . . . . . . . . . . . . . . . . . . . .139
8-12 ICG Multiplier Register (ICGMR) . . . . . . . . . . . . . . . . . . . . . .141
8-13 ICG Trim Register (ICGTR) . . . . . . . . . . . . . . . . . . . . . . . . . .142
8-14 ICG DCO Divider Register (ICGDVR) . . . . . . . . . . . . . . . . . .143
8-15 ICG DCO Stage Register (ICGDSR) . . . . . . . . . . . . . . . . . . .144
9-1
Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . .146
10-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
10-2 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
10-3 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .154
10-4 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Advance Information
18
MC68HC908RFRK2
List of Figures
MOTOROLA
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FREESCALE [ Freescale ]
