Freescale Semiconductor, Inc.
Monitor Read-Only Memory (MON)
NEXT
START
BIT
START
BIT
STOP
BIT
$A5
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 4
BIT 5
BIT 5
BIT 6
BIT 6
BIT 7
BIT 7
1, 2, 3
STOP
BIT
START
BIT
NEXT
START
BIT
BREAK
BIT 0
BIT 1
BIT 2
BIT 3
Notes: 1 = Echo delay (2 bit times)
2 = Data return delay (2 bit times)
3 = Wait 1 bit time before sending next byte.
1, 2, 3
Figure 10-3. Sample Monitor Waveforms
10.4.3 Echoing
As shown in Figure 10-4, the monitor ROM immediately echoes each
received byte back to the PTA0 pin for error checking.
Any result of a command appears after the echo of the last byte of the
command.
SENT TO
MONITOR
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
1
3
1
3
1
2
ECHO
RESULT
Notes: 1 = Echo delay (2 bit times)
2 = Data return delay (2 bit times)
3 = Wait 1 bit time before sending next byte.
Figure 10-4. Read Transaction
10.4.4 Break Signal
A start bit followed by nine low bits is a break signal. (See Figure 10-5.)
When the monitor receives a break signal, it drives the PTA0 pin high for
the duration of two bits before echoing the break signal.
Advance Information
154
MC68HC908RFRK2
Monitor Read-Only Memory (MON)
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
