Freescale Semiconductor, Inc.
Monitor Read-Only Memory (MON)
10.4.1 Monitor Mode Entry
Table 10-1 shows the pin conditions for entering monitor mode.
Table 10-1. Monitor Mode Entry
Bus
Frequency
(2)
CGMOUT
CGMOUT
--------------------------
2
CGMXCLK
(1)
1
0
1
VHI
-----------------------------
2
1. For VHI, see 17.7 3.0-Volt DC Electrical Characteristics Excluding UHF Module and
17.3 Absolute Maximum Ratings.
2. If the high voltage (VHI) is removed from the IRQ1 pin while in monitor mode, the clock
select bit (CS) controls the source of CGMOUT.
Enter monitor mode by either:
•
•
Executing a software interrupt instruction (SWI), or
Applying a logic 0 and then a logic 1 to the RST pin
NOTE: Upon entering monitor mode, an interrupt stack frame plus a stacked H
register will leave the stack pointer at address $00F9.
Once out of reset, the MCU waits for the host to send eight security bytes
(see 10.4.7 Security). After the security bytes, the MCU sends a break
signal (10 consecutive logic 0s) to the host computer, indicating that it is
ready to receive a command.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt.
The alternate vectors are in the $FE page instead of the $FF page and
allow code execution from the internal monitor firmware instead of user
code. The COP module is disabled in monitor mode as long as V (see
HI
Section 17. Preliminary Electrical Specifications) is applied to either
the IRQ1 pin or the RST pin. (See Section 6. System Integration
Module (SIM) for more information on modes of operation.) The ICG
module is bypassed in monitor mode as long as V is applied to the
HI
IRQ1 pin. RST does not affect the ICG.
Advance Information
152
MC68HC908RFRK2
Monitor Read-Only Memory (MON)
MOTOROLA
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